1. Field of the Invention
The invention relates in general to a memory control circuit and an associated control method, and more particularly to a dynamic memory signal phase tracking method and an associated control circuit.
2. Description of the Related Art
A memory controller, generally connected to a memory module, writes data into the memory module or reads data from the memory module. One of the most common memory modules is a double data rate (DDR) memory module.
When the memory controller issues a write command, data can be sent from the memory controller to the memory module to be stored therein. When the memory controller issues a read command, data can be sent from the memory module to the memory controller for subsequent processes.
FIG. 1 shows a schematic diagram of connections between a memory controller and a memory module. Signals between a memory controller 100 and a DDR memory module 200 at least include an external clock CLKext, address signals, a command signal, serial data signals DQ0 to DQ7, and a data strobe signal DQS. The command signal includes a write enable signal WE, the address signals include memory address signals A0 to A13, a row address strobe signal RAS and a column address strobe signal CAS.
A DDR transaction includes the following steps. The memory controller 100 first issues the command signal and the address signals, and the DDR module 200 obtains a command according to the command signal and the address signals. The command signal may be a write command or a read command. The DDR memory module 200 then stores or outputs data according to the command.
When the command is a write command, the serial data signals DQ0 to DQ7 and the data strobe signal DQS are generated by the memory controller 200. Thus, the DDR memory module 200 latches data on the serial data signals DQ0 to DQ7 according to the data strobe signal DQS generated by the memory controller 100, and writes the latched data into corresponding memory addresses in the DDR memory module 200.
A period from the memory module 200 receives the read command to a time point where data is ready for output is referred to as a column address strobe (CAS) latency CL. Take an example of CL=2. When the command is a read command, the DDR memory module 200 only drives the serial data signals DQ0 to DQ7 after two periods of the external clock CLKext. At this point, the memory controller 100 may latch the serial data signals DQ0 to DQ7 according to the data strobe signal DQS and obtain data in the corresponding memory addresses.
FIG. 2 shows a signal timing diagram when reading a command. In general, when the DDR memory module 200 outputs data, the data strobe signal DQS and the serial data signals DQ0 to DQ7 are generated. At this point, a frequency of the data strobe signal DQS is the same as that of the external clock signal CLKext. Conversely, before the DDR memory module 200 outputs data, the data strobe signal DQS is in a high-impedance tri-state.
As observed from FIG. 2, at a time point T0, the memory addresses A0 to A13 and the read command Read are obtained from the address signal and the command signal, whereas a no operation command NOP is obtained at other time points. The CAS latency CL is two external clock CLKext periods (CL=2). Thus, the data strobe signal DQS changes from a tri-state to a low level at the time point T1, alternates between high and low levels between time points T2 and T4, and again changes to a tri-state at the time point T4. After the CAS latency of two external clocks CLXext (CL=2), data D0, D1, D2 and D3 is sequentially generated on the serial data signals DQ0 to DQ7 from the time point T2 to the time point T4. As such, the memory controller 100 may latch the data D0, D1, D2 and D3 on the serial data signals DQ0 to DQ7 according to rising and falling edges of the data strobe signal DQS.
Theoretically, the memory controller 100 may delay the phase of the received data strobe signal DQS by 90 degrees to latch the serial data signals DQ0 to DQ7. However, due to variations and errors in a layout of a printed circuit board, and manufacturing processes and voltages of circuits in the memory controller 100, as well as other external factors (e.g., the ambient temperature), memory signals may be caused to drift, e.g., the serial data signals DQ0 to DQ7 are caused to drift. As a result, the serial data signals DQ0 to DQ7 may not be normally accessed after the phase of the data strobe signal DQS is delayed by 90 degrees.
FIG. 3 shows a schematic diagram of an eye pattern of the serial data signal DQ and the data strobe signal DQS received by the memory controller 100. Due to the drift in the memory signals, the memory controller 100 is required to set an optimal delay phase of the data strobe signal DQS before its normal operations begin, so that the data strobe signal DQS may correctly latch the serial data signal DQ. In other words, before the memory controller 100 enters a normal operation mode, the memory controller 100 needs to perform a scanning test to establish a DQS latch interval of the data strobe signal DQS.
When performing the scanning test, the memory controller 100 gradually changes the delay phase of the data strobe signal DQS and accordingly accesses data in the DDR memory module 200. As shown in FIG. 3, when the delay phase of the data strobe signal DQS is between t1 and t2, the data in the DDR memory module 200 can be correctly accessed. A range as the delay period between t1 and t2 is referred to as a DQS latching interval.
Having confirmed the DQS latching interval, the optimal delay phase of the data strobe signal DQS can be accordingly set to ta, where ta=(t1+t2)/2. That is, the data strobe signal DQS is set to a center of the DQS latching interval, thereby ensuring the memory controller 100 to correctly access the data in the DDR memory module 200 when the memory controller 100 operates in the normal operation mode. When the phase setting of the data strobe signal DQS is complete, the entire system is then allowed to be activated to enter the normal operation mode.
In actual situations, when the entire system continues working, different system loads affects internal currents and temperature distributions in the circuits, and even a situation with drastic fluctuations in the ambient temperature may affect the quality of signals between the memory controller 100 and the DDR memory module 200, causing the memory signals to drift more severely. At this point, the DQS latching interval may be shifted or even reduced.
In the prior art, before normal operations are activated, the optimal delay phase of the data strobe signal DQS is set and cannot be modified. Thus, when the entire system continues working, in response to the change in the DQS latching interval, the data strobe signal DQS may fail to access the data in the DDR memory module 200 according to the previously set optimal phase delay.